Dear All,
It seems that the simulation of PORT on ATMega328 does not work as expected. In particular, I have noticed that regardless of the DDRx register the PORTx i can READ from the PORTx. The expected behavior is that READ operation is working only when DDRx is configured as INPUT.
I have attached the SimulIDE circuit and the Firmware SourceCode, as you can read in the comment whtever you comment line 13 the code works
Am i doing something wrong or there is an issue with SimulIDE simulating the ATMega328 ?
Ciao,
Stefano
It seems that the simulation of PORT on ATMega328 does not work as expected. In particular, I have noticed that regardless of the DDRx register the PORTx i can READ from the PORTx. The expected behavior is that READ operation is working only when DDRx is configured as INPUT.
I have attached the SimulIDE circuit and the Firmware SourceCode, as you can read in the comment whtever you comment line 13 the code works
Am i doing something wrong or there is an issue with SimulIDE simulating the ATMega328 ?
Ciao,
Stefano
- Attachments
- main.zip
- Assembly source code
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- AccendiScale.zip
- SimulIDE circuit
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- (2 Kb) Downloaded 2 times