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AVR Timer1 and Timer2 interference?

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1AVR Timer1 and Timer2 interference?  Empty AVR Timer1 and Timer2 interference? Wed Jan 12, 2022 3:35 am

TimFisch

TimFisch

In a setup, we use two timer of the AVR 328 in order to drive a fullbridge (one TC per half bridge). There seem to be problems in handling the pin access once both timer are used.

Seen on V1.0.0. R815 WIN10

Situation 1:

  1. Timer1 is initializes
  2. Timer2 not
  3. DDR register is set for both OCR Pins (B1 und B3)
  4. in the endless loop:
  5. turn on Timer1 (PB1 given by timer)
  6. toggle PB3
  7. turn off Timer1 (PB1 given by PORTB)
  8. toggle PB1
  9. repeat


This works fine. The problem appears, when step 5. and 7. is changed a bit:

Situation 2:

  1. Timer1 is initializes
  2. Timer2 not
  3. DDR register is set for both OCR Pins (B1 und B3)
  4. in the endless loop:
  5. turn on Timer1 (PB1 given by timer), turn off Timer2 (PB3 given by PORTB)
  6. toggle PB3
  7. turn off Timer1 (PB1 given by PORTB), turn on Timer2 (PB3 given by timer)
  8. toggle PB1
  9. repeat


By this the toggling of PB3 and PB1 does not work all the time.

I made an example code for this:

Code:

#ifndef F_CPU
#define F_CPU 16000000UL        
#endif

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>


int main(void)
{
 TCCR1A = (1<<WGM10) ; //TC1 as Fast-PWM mode 8bit
 TCCR1B = (1<<CS10)  | (1<<WGM12); //no Prescaler
 OCR1A=128;
 
 //TCCR2A = (1<<WGM20) | (1<<WGM21) | (1<<COM2A1); //TC2 as Fast-PWM mode 8bit, Non Inverting
 //TCCR2B = (1<<CS20); // no Prescaler
 //OCR2A=128;
 
    sei(); //Global Interrupt Flag

 DDRB  = 0b00001010; //set PB1 and PB2 as output
    while (1)
    {
 //TCCR2A = TCCR2A & ~(1<<COM1A1); //uncomment this code
 TCCR1A = TCCR1A |  (1<<COM1A1); // Turn TC1 on  (PB1 set by Timer TC1)
 PORTB = 0b00000000; // clear PB3
 _delay_us(100);
 PORTB = 0b00001000; // set PB3
 _delay_us(100);
 //TCCR2A = TCCR2A |  (1<<COM1A1); //uncomment this code
 TCCR1A = TCCR1A & ~(1<<COM1A1); // Turn TC1 off (PB1 should be programmable with PORTB)
 PORTB = 0b00000000; // clear PB1
 _delay_us(100);
 PORTB = 0b00000010; // set PB1
 _delay_us(100);
    }
}


I am somehow not able to upload pics. I get an "Uploaded file is not valid: exceeded image dimensions limit (image size : [849 x 86], limit : [1 x 1])." I attached all necessary files (pics, hex, code, sim1)

thanks

This is the correct one:
AVR Timer1 and Timer2 interference?  Onlyon10

This one shows problems starting from the third repetition (lower signal does not show low between PWM, only high)
AVR Timer1 and Timer2 interference?  Bothti10
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AVR Timer1 and Timer2 interference?  AttachmentTimerSimuHexPicsAndCode.zip
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Last edited by arcachofo on Wed Jan 12, 2022 3:26 pm; edited 3 times in total (Reason for editing : Set as solved (green color))

https://wiki.mexle.hs-heilbronn.de/

arcachofo

arcachofo

I will have a look.

I am somehow not able to upload pics.
Pics as attachments are disabled.
But you can use the method described here:
https://simulide.forumotion.com/t383-how-to-add-pictures-and-attachnents-to-your-posts

TimFisch

TimFisch

Thanks for the tipp, I added the pics.

arcachofo likes this post

https://wiki.mexle.hs-heilbronn.de/

arcachofo

arcachofo

This one shows problems starting from the third repetition (lower signal does not show low between PWM, only high)
Is it random or just stops working after a few times?
Anyway I will have a look tomorrow.

EDIT:
By this the toggling of PB3 and PB1 does not work all the time.
I guess it is random then.

TimFisch

TimFisch

It leems to me, that is correlates with the last output given by the PWR: once the last output given by pwr was low --> both high an low can be set by PORTB. Once the last output given by pwr was high --> it is not possible to get the signal to low.

https://wiki.mexle.hs-heilbronn.de/

arcachofo

arcachofo

It leems to me, that is correlates with the last output given by the PWR: once the last output given by pwr was low --> both high an low can be set by PORTB. Once the last output given by pwr was high --> it is not possible to get the signal to low.
That's a good clue...

arcachofo

arcachofo

Issue solved at Rev 842.

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