Faulty Latch operation (Rev 331)

Thank you for your very fast bug fixes!

Working on Rev. 331.

The Latch Logic Component behaves in a strange fashion.

Connecting D0 to a 1 Hz clock and in IE mode, everything passes through no mater the value of IE:



Turning it to from IE to Clock, does not latch on any clock edge.

Moreover, Q0 initial simulation value is 1. I am not sure if this is by design (I think same holds for D Flip-Flop) or needs fixing.

Thank you once more,
Theodore K.

Hi.

It is working for me at Rev. 348.
Probably something was solved just by chance.

Just informing:
Tested it on Rev. 347 and problem remains.

Could not compile Rev. 348 due to avrport.h missing (I reported it in Development).

Let's hope 348 is OK.

Thank you!